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| DATA SHEET PD78P324, 78P324(A) 16-/8-Bit Single-Chip Microcomputers MOS INTEGRATED CIRCUIT The PD78P324 is a product in which the PD78324's internal mask ROM is replaced by a one-time PROM or EPROM. The one-time PROM product, which enables writing only once, is effective for multiple-device small production of sets or early start of mass-production. The EPROM product, which enables program writing, deletion, and rewriting, is the most suitable for system evaluation. The PD78P324(A) is more reliable than the PD78P324. The PD78P324(A) is a product resulting from the PD78324(A) whose internal mask ROM is replaced by a one-time PROM. For details of functions, please refer to the following User's Manual. Reading this manual is indispensable especially for designing work. PD78322 User's Manual: IEU-1248 FEATURES q PD78324 compatible * For mass-production, this can be replaced by the PD78324 incorporated in the mask ROM. q Minimum instruction run time: 250 ns (with the external clock operating at 16 MHz): PD78P324 & 78P324(A) 320 ns (with the external clock operating at 12.5 MHz): PD78P324(A1) & 78P324(A2) q Internal PROM: 32768 x 8 bits * Writing enabled only once (windowless one-time PROM product) * Elimination by ultraviolet light and electrical rewriting enabled (EPROM product with window): PD78P324 only q ECC circuit incorporated * High internal PROM content reliablility possible q PROM programming characteristic: PD27C1001A compatible q QTOPTM microcomputer compatible Remark A QTOP microcomputer is a single-chip microcomputer with one-time PROM for which program writing, marking, screening, and verifying is completely supported by NEC. APPLICATION FIELDS q PD78P324: Fields dealing with motor control equipment. q PD78P324(A), 78P324(A1), and 78P324(A2): Automotive and transportation equipments, etc. This document describes the PD78P324, 78P324(A), PD78P324(A1), and PD78P324(A2) as well. However, unless there are particular differences, the PD78P324 is described as a representative product. PROM is the representative term used for the part common to both the one-time PROM product and the EPROM product. The information in this document is subject to change without notice. Document No. IC-2857 (O. D. No. IC-8315) Date Published January 1995 P Printed in Japan (c) 1991, 1995 PD78P324, 78P324(A) ORDERING INFORMATION Part No. Package 74-pin plastic QFP(20 x 20 mm) 68-pin plastic QFJ(s 950 mil) s 68-pin ceramic WQFN 74-pin ceramic WQFN 74-pin plastic QFP(20 x 20 mm) 74-pin plastic QFP(20 x 20 mm) 74-pin plastic QFP(20 x 20 mm) 68-pin plastic QFJ(s 950 mil) s 68-pin plastic QFJ(s 950 mil) s 68-pin plastic QFJ(s 950 mil) s Internal ROM One-time PROM One-time PROM EPROM EPROM One-time PROM One-time PROM One-time PROM One-time PROM One-time PROM One-time PROM Operating Temperature (TA) -10 to +70 C -10 to +70 C -10 to +70 C -10 to +70 C -40 to +85 C -40 to +110 C -40 to +125 C -40 to +85 C -40 to +110 C -40 to +125 C PD78P324GJ-5BJ PD78P324LP PD78P324KC PD78P324KD PD78P324GJ(A)-5BJ PD78P324GJ(A1)-5BJ PD78P324GJ(A2)-5BJ PD78P324LP(A) PD78P324LP(A1) PD78P324LP(A2) QUALITY GRADE Part No. Quality Grade Standard Standard Standard Standard Special Special Special Special Special Special PD78P324GJ-5BJ PD78P324LP PD78P324KC PD78P324KD PD78P324GJ(A)-5BJ PD78P324GJ(A1)-5BJ PD78P324GJ(A2)-5BJ PD78P324LP(A) PD78P324LP(A1) PD78P324LP(A2) Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 PD78P324, 78P324(A) DIFFERENCES AMONG PD78P324, 78P324(A), 78P324(A1), AND 78P324(A2) Product Name Parameter Quality grade Operating ambient temperature (TA) Operating frequency Minimum instruction execution time Permissible pin injection current characteristics on overvoltage application DC characteristics AC characteristics A/D converter characteristics One-time PROM product EPROM product Provided Standard -10 to +70 C -40 to +85 C Special -40 to +110 C -40 to +125 C PD78P324 PD78P324(A) PD78P324(A1) PD78P324(A2) 8 to 16 MHz 250 ns (when operated at 16 MHz) 8 to 12.5 MHz 320 ns (when operated at 12.5 MHz) None Provided Differ in the analog pin input leak current, the VDD supply current, and the data retention current. Differ in the bus timing. Differ in the analog input voltage and the A/D converter data retention current. Provided None 3 PD78P324, 78P324(A) PIN CONFIGURATION (Top View) (1) Normal operation mode (a) 74-pin plastic QFP(20 x 20 mm); 74-pin ceramic WQFN P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR P92/TAS P93/TMD VSS EA P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1 NC 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 NC P56/A14 P57/A15 VDD AVSS P70/AN0 P71/AN1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PO0/RTP0 WDTO VSS NC X1 X2 RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 NC P34/SCK P33/SI/SB1 P32/SO/SB0 P31/RXD P30/TXD Caution As a measure against noise, please connect the NC pin to VSS. (It is also possible to leave this pin unconnected.) Remark Pin-compatible with PD78324GJ. 4 NC P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVREF AVDD VDD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 P26/INTP5 P27/INTP6 NC PD78P324GJ(A2)-5BJ PD78P324GJ-5BJ PD78P324GJ(A1)-5BJ PD78P324GJ(A)-5BJ PD78P324KD PD78P324, 78P324(A) (b) 68-pin plastic QFJ(s 950 mil); 68-pin ceramic WQFN s P27/INTP6/T1 P26/INTP5 P25/INTP4 P24/INTP3 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P30/TXD P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 P72/AN2 AVREF AV DD VDD P71/AN1 P70/AN0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 PD78P324LP PD78P324KC PD78P324LP(A) PD78P324LP(A1) PD78P324LP(A2) 54 53 52 51 50 49 48 47 46 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P93/TMD P91/WR P90/RD ASTB P40/AD0 P41/AD1 P01/RTP1 P02/RTP2 P03/RTP3 P04/RTP4 P05/RTP5 P06/RTP6 P07/RTP7 Remark Pin-compatible with PD78324LP. P42/AD2 P92/TAS VSS EA 5 PD78P324, 78P324(A) P00-P07 P20-P27 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 NMI INTP0-INTP6 RTP0-RTP7 TI TXD RXD SB0/SO SB1/SI SCK TO00-TO03 TO10, TO11 : Port0 : Port2 : Port3 : Port4 : Port5 : Port7 : Port8 : Port9 : Nonmakable Interrupt : Interrupt from Peripherals : Realtime Port : Timer Input : Transmit Data : Receive Data : Serial Bus/Serial Output : Serial Bus/Serial Input : Serial Clock : Timer Output : RESET X1, X2 WDTO EA TMD TAS WR RD ASTB AD0-AD7 A8-A15 AN0-AN7 AVREF AVSS AVDD VDD VSS NC : Reset : Crystal : Watchdog Timer Output : External Access : Turbo Mode : Turbo Access Strobe : Write Strobe : Read Strobe : Address Strobe : Address/Data Bus : Address Bus : Analog Input : Analog Reference Voltage : Analog VSS : Analog VDD : Power Supply : Ground : Non-connection 6 PD78P324, 78P324(A) (2) PROM programming mode (RESET = H, AVDD = L) (a) 74-pin plastic QFP (20 x 20 mm); 74-pin ceramic WQFN D2 D1 D0 (Open) (L) D3 D4 D5 D6 D7 (L) NC (L) VDD (G) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 1 55 2 54 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VSS VPP A7 A6 A5 A4 A3 A2 A1 NC A0 (Open) VSS NC (G) (Open) RESET A14 A13 A12 A11 A10 A8 NC A16 A15 PGM CE OE AVDD VDD A9 PD78P324GJ(A2)-5BJ PD78P324GJ-5BJ PD78P324GJ(A1)-5BJ PD78P324GJ(A)-5BJ PD78P324KD NC (G) (G) Cautions 1. Codes marked by brackets refer to processing by pins unused in PROM programming mode. L G Open : Connect to VSS individually via a resistor. : Connect to VSS. : Do not connect anything. 2. As a measure against noise, please connect the NC pin to VSS. (It is also possible to leave this pin unconnected.) (L) NC 7 PD78P324, 78P324(A) (b) 68-pin plastic QFJ(s 950 mil); 68-pin ceramic WQFN s AVDD (G) VDD A9 (G) (L) 9 8 7 OE CE PGM A15 A16 A8 A10 A11 A12 A13 A14 RESET (Open) (G) VSS (Open) A0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD (G) PD78P324LP PD78P324KC PD78P324LP(A) PD78P324LP(A1) PD78P324LP(A2) 54 53 52 51 50 49 48 47 46 45 D7 D6 D5 D4 D3 (L) 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 (Open) A1 A2 A3 A4 A5 A6 A7 VPP VSS D0 D1 Caution Codes marked by brackets refer to processing by pins unused in PROM programming mode. L G : Connect to VSS individually via a resistor. : Connect to VSS. Open : Do not connect anything. A0-A16 D0-D7 CE OE PGM : Address Bus : Data Bus : Chip Enable : Output Enable : Programming Mode RESET AVDD VPP NC : Programming Mode Set : : Programming Power Supply : Non-connection 8 (L) D2 INTERNAL BLOCK DIAGRAM EXU Main RAM (P20) NMI INTP0-INTP5 (P21-P26) PROGRAMMABLE INTERRUPT CONTROLLER GENERAL REGISTERS 128 bytes & DATA MEMORY 128 bytes PROM Peripheral RAM BCU ALU 32K bytes 768 bytes (P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) T1/INTP6 SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL X1 X2 RESET ASTB RD WR TAS TMD EA/VPP* A8-A15 (P50-P57) AD0-AD7 (P40-P47) A0-A16* D0-D7* PGM* CE* OE* TINER/COUNTER UNIT (REAL TIME PULSE UNIT) MICRO SEQUENCE CONTROL MICRO ROM ECC (P34) SCK (P32) SO/SB0 (P33) SI/SB1 (P30) TXD (P31) RXD AN0-AN7 (P70-P77) AVREF AVSS AVDD WDTO 2 VDD 2 VSS P00-P07 (REALTIME PORT) P20-P27 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 SERIAL INTERFFACE (SBI) (UART) A/D CONVERTER (10 BITS) WDT PORT PD78P324, 78P324(A) Remark *: When in PROM programming mode 9 PD78P324, 78P324(A) TABLE OF CONTENTS 1. LIST OF PIN FUNCTIONS ........................................................................................................... 1.1 1.2 1.3 NORMAL OPERATION MODE ........................................................................................................... PROM PROGRAMMING MODE (RESET = H, AVDD = L) ................................................................. PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING ....................................................................... 11 11 13 14 2. 3. DIFFERENCE BETWEEN PD78P324 AND PD78324 .............................................................. PROM PROGRAMMING .............................................................................................................. 3.1 3.2 3.3 OPERATION MODE ............................................................................................................................ PROCEDURE FOR PROM WRITE ...................................................................................................... PROCEDURE FOR PROM READ ........................................................................................................ 16 17 18 19 21 4. 5. 6. 7. 8. 9. ERASURE CHARACTERISTICS (PD78P324KC/KD ONLY) ..................................................... ERASURE WINDOW SEAL (PD78P324KC/KD ONLY) ........................................................... ONE-TIME PROM PRODUCT SCREENING ................................................................................ ELECTRICAL SPECIFICATIONS .................................................................................................. PACKAGE DRAWINGS ................................................................................................................ RECOMMENDED SOLDERING CONDITIONS ........................................................................... 22 22 22 23 65 69 APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE INSTALLATION PATTERN .................................. APPENDIX B. TOOLS ......................................................................................................................... B.1 B.2 B.3 DEVELOPMENT TOOLS ..................................................................................................................... EVALUATION TOOLS ........................................................................................................................ EMBEDDED SOFTWARE .................................................................................................................... 71 73 73 77 77 10 PD78P324, 78P324(A) 1. 1.1 LIST OF PIN FUNCTIONS NORMAL OPERATION MODE (1) Port pins Pin Name I/O Function Port 0. 8-bit I/O port. I/O specifiable per bit. (Operable as a real-time output port as well.) Shared Pin Name P00-P07 I/O RTP0-RTP7 P20 P21 P22 P23 Input P24 P25 P26 P27 P30 P31 P32 P33 P34 P40-P47 I/O Port 4. 8-bit I/O port. I/O specifiable in units of eight bits. Port 5. 8-bit I/O port. I/O specifiable per bit. Port 7. 8-bit input-only port. I/O Port 3. 5-bit I/O port. I/O specifiable per bit. Port 2. 8-bit input-only port. NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6/TI TXD RXD SO/SB0 SI/SB1 SCK AD0-AD7 P50-P57 I/O A8-A15 P70-P77 P80 P81 P82 Input AN0-AN7 TO00 TO01 I/O P83 P84 P85 P90 P91 I/O P92 P93 Port 8. 6-bit I/O port. I/O specifiable per bit. TO02 TO03 TO10 TO11 RD Port 9. 4-bit I/O port. I/O specifiable per bit. WR TAS TMD 11 PD78P324, 78P324(A) (2) Pins other than ports (1/2) Pin Name RTP0-RTP7 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 NMI TI RXD TXD SI SO SB0 I/O SB1 SCK AD0-AD7 A8-A15 RD Output WR TAS Output TMD TO00 TO01 TO02 Output TO03 TO10 TO11 Output from the real-time pulse unit. P83 P84 P85 Write signal output to external memory. Control signal output for accessing the turbo access manager (PD71P301)Note. P91 P92 P93 P80 P81 P82 I/O I/O Output Input Input Input Output Input Output Non-maskable interrupt request input of edge detection. A valid edge can be selected by the external interrupt mode register. External counter clock input to Timer 1 (TM1). Serial data input of the asynchronous serial interface (UART). Serial data output of the asynchronous serial interface (UART). Serial data input in three-wire mode of the clock synchronous serial interface. Serial data input in three-wire mode of the clock synchronous serial interface. Serial data output in three-wire mode of the clock synchronous serial interface. Serial clock I/O of the clock synchronous serial interface. Address data bus for accessing external memory. Address bus for accessing external memory. Read signal output to external memory. Input External interrupt request input of edge detection. A valid edge can be selected by the external interrupt mode register. I/O Output Function Real-time output port performing pulse outputs synchronously with the trigger symbols from the real-time pulse unit (RPU). Shared Pin Name P00-P07 P21 P22 P23 P24 P25 P26 P27/TI P20 P27/INTP6 P31 P30 P33/SB1 P32/SB0 P32/SO P33/SI P34 P40-P47 P50-P57 P90 Note The turbo access manager (PD71P301) is a maintenance product. 12 PD78P324, 78P324(A) (2) Pins other than ports (2/2) Pin Name ASTB I/O Output Function Access to external memory. Timing signal output for externally latching the lower address which is output from the AD0-AD7 pin. Output of the signal which indicates that the watchdog timer generated a non-maskable interrupt. Normally, the EA pin is connected to VDD. By connecting the EA pin to Vss, the system is placed in ROM-less mode to access external memory. The level of the EA pin cannot be switched over during operation. Analog input to the A/D converter Reference voltage input of the A/D converter. Analog power of the A/D converter. Ground of the A/D converter. Input of the system reset. Connection of the crystal oscillator for system clock generation. When clocks are supplied externally, they are input to the X1 pin and their reverse signals are input to the X2 pin. (The X2 pin can also be left unconnected.) Positive power voltage. Ground. Internally unconnected. Please connect this to Vss. (It can also be left unconnected.) Shared Pin Name -- WDTO Output -- EA Input -- AN0-AN7 AVREF AVDD AVSS RESET X1 X2 VDD VSS NC Input Input -- -- Input Input -- -- -- -- P70-P77 -- -- -- -- -- -- -- -- -- 1.2 PROM PROGRAMMING MODE (RESET = H, AVDD = L) Pin Name AVDD Input RESET A0-A16 D0-D7 PGM CE OE VPP VDD -- VSS NC Ground Internally unconnected. Please connect this to VSS. (It can also be left unconnected.) Input I/O Input Input Input Address bus Data bus Program input PROM enable input Read strobe to PROM Write power Positive power voltage PROM programming mode setting I/O Function 13 PD78P324, 78P324(A) 1.3 PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING The I/O circuits of the pins are shown in Table 1-1 and Figure 1-1 some of them in a simplified form. Table 1-1. I/O Circuit Types of Pins and Recommended Connection Methods When Unused Pin Name P00/RTP0-P07/RTP7 P20/NMI P21/INTP0-P26/INTP5 P27/INTP6/TI P30/TXD P31/RXD P32/SO/SB0 P33/SI/SB1 P34/SCK P40/AD0-P47/AD7 P50/A8-P57/A15 P70/AN0-P77/AN7 P80/TO00-P83/TO03 P84/TO10, P85/TO11 P90/RD P91/WR P92/TAS P93/TMD WDTO ASTB EA RESET AVDD AVREF AVSS VPP NC 3 No connection required. 4 1 2 -- -- -- -- -- -- Connected to VDD. Connected to VSS. Connected to VDD. Connected to VSS. (It is also possible to leave this unconnected.) 5 5 9 5 Input status: Connected to VDD or Vss via a resistor individually. Output status: No connection required. Connected to Vss. 8 Input status: Connected to VDD or VSS via a resistor individually. Output status: No connection required. 5 2 Connected to VSS. I/O Circuit Type 5 Recommended Connection Method When Unused Input status: Connected to VDD or VSS via a resistor individually. Output status: No connection required. 14 PD78P324, 78P324(A) Figure 1-1. I/O Circuits of Pins Type 1 Type 5 data P-ch IN N-ch output disable N-ch VDD P-ch IN/OUT VDD input disable Type 2 Type 8 data IN VDD P-ch IN/OUT output disable N-ch This is a Schmitt-triggered input which has the hysteresis characteristic. Type 3 VDD P-ch OUT N-ch Vref (Threshold voltage) Type 9 P-ch IN N-ch Comparator input enable Type 4 data VDD P-ch OUT output disable N-ch This is the push-pull input which is capable of output highimpedance (off for both P-ch and N-ch). 15 PD78P324, 78P324(A) 2. DIFFERENCES BETWEEN PD78P324 AND PD78324 The PD78P324 is a product in which the PD78324's internal mask ROM is replaced by a 32KB PROM. Therefore, these two products share the same functions, except for differences deriving from the ROM specifications (for example, Write and Verify, etc.). Their differences are shown in Table 2-1 below. Table 2-1. Differences between PD78P324 and PD78324 Product Name Parameter Internal program memory (Electric write) ECC circuit PROM programming pin Package Electrical characteristics Others * 68-pin plastic QFJ * 74-pin plastic QFP One-time PROM (Write enabled only once) With With * 68-pin ceramic WQFN * 74-pin ceramic WQFN EPROM (Rewrite enabled) Mask ROM Without Without * 68-pin plastic QFJ * 74-pin plastic QFP PD78P324 PD78324 Differ in current consumption, etc. As they differ in their circuit size and mask layout, their noise resistance volume and noise reflection differ. Cautions 1. The PROM product and the mask ROM product differ in their noise resistance volume and noise reflection. If replacement of the PROM product with the mask ROM product in the process of trial to mass production is being considered, ensure to make a sufficient evaluation with the CS product (not ES product) of the mask ROM product. 2. The PD78P324(A)/(A1)/(A2) are one-time PROM products only. The differences between the PD78P324(A)/(A1)/(A2) and the PD78324(A)/(A1)/(A2) are the same as those shown in the table above, except in terms of the EPROM product. 16 PD78P324, 78P324(A) 3. PROM PROGRAMMING The PD78P324 incorporates an electrically writable 32768-by-8-bit program PROM and an 8192-by-6-bit ECC (error correcting code) PROM. ECC corrects the errors in codes written in the program PROM, thus improving the reliability of the PROM content. Figure 3-1 shows the memory map in programming mode. Figure 3-1. Memory Map in Programming Mode A004H A003H A000H 9FFFH ECC (for ECW) ECW (4 x 8) PROM for ECCNote (8192 x 6) 8000H 7FFFH Program PROM (32768 x 8) 0000H Note On the ECC PROM, the lower 6 bits are valid. When programming, set the RESET pin and the AVDD pin to PROM programming mode. The programming characteristics of the PD78P324 are compatible with the PD27C1001A. However, the programming mode is compatible only with the byte program mode of the PD27C1001A. For setting on the PROM programmer, please select the byte program mode of the 27C1001A mode. When using the ECC circuit, reset the lowest bit (A000.0) of the lowest byte of the ECW (ECC control word) to enable the operation of the ECC circuit. ECW is a 4-byte register which controls the operation of the ECC circuit. ECC and ECW are generated automatically with the ECCGEN (ECC generator) which comes with the RA78K3 assembler package. (ECC is generated in the lower 6 bits; and the upper 2 bits are fixed to 1.) 17 PD78P324, 78P324(A) Table 3-1. Pin Functions in Programming Mode Function Address input Data input Program pulse Chip enable Output enable Program voltage Mode voltage Normal Operation Mode P00-P07, P80, P20, P81-P85, P33, P34 P40-P47 P32 P31 P30 VPP RESET, AVDD Programming Mode A0-A16 D0-D07 PGM CE OE 3.1 OPERATION MODE When placing the microcomputer in programming Write/Verify mode, set it to RESET = H and AVDD = L. In this mode, an operation mode in Table 3-2 can be selected by further setting the CE and OE pins. When reading the content of the PROM, set it to Read mode. Process the unused pins in accordance with the instructions in the PIN CONFIGURATION. Table 3-2. Operation Mode of PROM Programming Mode Program Write Program verify Program inhibit Read Output disable Standby RESET AVDD CE L L X H L X L L H OE H L L H L H X PGM L H +12.5 V L H H X X +5 V +5 V +6.5 V High impedance Data output High impedance High impedance VPP VDD D0-D7 Data input Data output Remark x: L or H 18 PD78P324, 78P324(A) 3.2 PROCEDURE FOR PROM WRITE The procedure for writing into the PROM is as follows (see Figure 3-3). (1) Fix to RESET = H; and AVDD = L. Other unused pins are processed as directed by the PIN CONFIGURATION. (2) Supply +6.5 V to the VDD pin; and +12.5 V to the VPP pin. Enter the low level into the CE pin. (3) Enter the initial address into A0-A16. (4) Enter the Write data into D0-D7. (5) Enter the 0.1 ms program pulse (active low) into the PGM pin. (6) Verify mode. Check if the Write data has been written or not. Enter the active low pulse into the OE pin and read the Write data from D0-D7. * When written: Move to (8). * When not able to write: Repeat (4) to (6). If it is not possible to write even when the repetition has been made ten times, move to (7). (7) Stop the Write operation as a defective device. (8) Increment the address. (9) Repeat (4) to (8) until the final address. The timing of the above (2) to (7) steps is shown in Figure 3-2. Figure 3-2. PROM Write/Verify Timing Program A0-A16 Program verify Address input D0-D7 Hi-Z Data input Hi-Z Data output Hi-Z + 12.5V VPP VDD + 6.5V VDD VDD CE (input) PGM (input) OE (input) 19 PD78P324, 78P324(A) Figure 3-3. Write Procedure Flowchart (1) Start writing (2) Supply the supply voltage (3) Supply the initial address (4) Supply the Write data (5) Supply the program pulse Write disabled ( 10th times ) Verify mode Write OK (6) Write disabled ( less than 10 times ) (8) Address increment (9) Final address >Final address (7) Defective device Final address (10) Write complete 20 PD78P324, 78P324(A) 3.3 PROCEDURE FOR PROM READ The PROM content is read to the external data bus (D0-D7) in accordance with the following procedure: (1) Fix to RESET = H; and AVDD = L. Other unused pins are processed as directed by the PIN CONFIGURATION. (2) Supply +5 V to the VDD and VPP pins. (3) Enter the address of the data read into the A0-A16 pin. (4) Read mode (CE = L; OE = L) (5) Data is output to the D0-D7 pin. The timing of the above (2) to (5) is shown in Figure 3-4. Figure 3-4. PROM Read Timing A0-A14 Address input CE (input) OE (input) Hi-Z D0-D7 Data output Hi-Z 21 PD78P324, 78P324(A) 4. ERASURE CHARACTERISTICS (PD78P324KC/KD ONLY) The PD78P324KC/KD can erase (FFH) the content of the data written in the program memory and perform rewriting. The data content is erased by radiating light with a wavelength shorter than about 400 nm on the erasure window. Normally, ultraviolet light with a wavelength of 254 nm is radiated. The volume of light required for erasing the data content completely is as follows: * Ultraviolet ray intensity x erasure time: 15 W*s/cm2 or more * Erasure time: 15 to 20 mins (This is so when using an ultraviolet lamp of 12,000 W/cm2. However, a longer time may be required due to performance degradation of the ultraviolet ray lamp or dirt deposited on the erasure window, etc.) For erasure, make sure to place the ultraviolet ray lamp at a location within 2.5 cm from the erasure window. If the ultraviolet ray lamp is equipped with a filter, make sure that the filter is removed for radiation. 5. ERASURE WINDOW SEAL (PD78P324KC/KD ONLY) If the erasure window part of the PD78P324KC/KD is exposed to sunlight or fluorescent light for too long, the EPROM data may be erased or the internal circuits may malfunction. To prevent such an accident, please ensure that the erasure window part is covered with a protective seal except when the data is going to be erased. The EPROM package with window is shipped with a protective seal that is NEC's guarantee of quality. 6. ONE-TIME PROM PRODUCT SCREENING Structurally, it is not possible for NEC to test the one-time PROM products (PD78P324GJ-5BJ/(A)/(A1)/ (A2) and 78P324LP/(A)/(A1)/(A2) completely before shipment. Therefore, it recommended that, after writing the required data, the screening be implemented to verify the PROM after storing the product in the following temperature and condition. Storage Temperature 125 C Storage Time 24 hrs NEC provides at a charge services including the one-time PROM writing, sealing, screening and verifying under the title of QTOP microcomputer. For further details, please contact an NEC salesperson. 22 PD78P324, 78P324(A) 7. ELECTRICAL SPECIFICATIONS (1) PD78P324 Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 C) Parameter Symbol VDD AVDD Supply voltage VPP AVSS Input voltage Output voltage Low-level output current VI VO All output pins IOL Total of all output pins All output pins High-level output current IOH Total of all output pins AVDD > VDD Analog input voltage VIAN Note 2 VDD AVDD AVDD > VDD A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF TA Tstg VDD AVDD -20 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -10 to +70 -65 to +150 C C mA 90 -1.0 mA mA Note 1 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 4.0 V V V V mA Condition Rating -0.5 to +7.0 -0.5 to VDD +0.5 Unit V V Notes 1. Except P70/AN0-P77/AN7. 2. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. Recommended Operating Range Oscillation Frequency 8MHz fXX 16MHz TA -10 to +70 C VDD +5.0 V 10 % Capacitance (TA = 25 C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz; 0 V except measured pins Condition MIN. TUP. MAX. 10 20 20 Unit pF pF pF 23 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (2/9) Oscillator Characteristics (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Oscillator Recommended Circuit Parameter MIN. MAX. Unit X2 X1 VSS Ceramic oscillator or crystal oscillator C2 C1 Oscillation frequency (fXX) 8 16 MHz X1 X2 HCMOS inverter X1 input frequency (fX) 8 16 MHz External clock X1 or X2 No connection required HCMOS inverter X1 input rise time, fall time (tXR, tXF) X1 input high-/low-level width (tWXH, tWXL) 0 25 20 80 ns ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. * Make the wiring as short as possible. * Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. * Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. * Do not fetch signals from the oscillation circuit. 24 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (3/9) Recommended Oscillation Circuit Constants Ceramic Oscillator Recommended Constant Manufacturer Product Name CSA8.00MT CSA12.0MT CSA14.74MXZ040 Murata Mfg. Co., Ltd. CSA16.00MX040 CST8.00MTW CST12.0MTW CST14.74MXW0C3 CST16.00MXW0C3 Frequency (MHz) C1 (pF) 8.0 12.0 14.74 16.0 8.0 12.0 14.74 16.0 Incorporated Incorporated 30 C2 (pF) 30 15 15 25 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (4/9) DC Characteristics (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Low-level input voltage High-level input voltage VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current IDD2 Data retention voltage Data retention current IDDDR STOP mode VDDDR=5.0 V10% 10 50 VDDDR HALT mode STOP mode VDDDR = 2.5 V 2.5 2 10 35 55 mA V VOL VOH ILI ILIAN ILO IDD1 Note 3 Note 4 Note 2 IOL = 2.0mA IOH = -400A 0 V VI VDD 0 V VIAN AVREF VDD-1.0 10 10 10 70 95 0.8 VDD 0.45 V V Symbol VIL VIH1 Note 1 Condition MIN. 0 2.2 V TYP. MAX. 0.8 Unit V A A A mA 0 V VO VDD Operation mode A A Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 26 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (5/9) AC Characteristics (TA = -10 to +70 C, VDD = +5 V 10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter System clock cycle time Address setup time (vs. ASTB ) Address hold time (vs. ASTB ) Address RD delay time RD address float time Address data input time RD data input time ASTB RD delay time Data hold time (vs. RD ) RD address active time RD low-level width ASTB high-level width Address WR delay time ASTB data output time WR data output time ASTB WR delay time Data setup time (vs. WR ) Data hold time (vs. WR ) WR ASTB delay time WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 42 147 32 42 147 42 0 50 147 37 85 102 40 Condition MIN. 125 32 32 85 10 222 112 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 27 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Symbol tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation formula 0.5T-30 0.5T-30 T-40 (2.5+n) T-90 (1.5+n) T-75 0.5T-20 0.5T-12 (1.5+n) T-40 0.5T-25 T-40 0.5T+40 0.5T-20 1.5T-40 0.5T-30 0.5T-20 (1.5+n) T-40 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 28 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (7/9) Serial Operation (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Serial clock cycle time Symbol SCK output tCYSK SCK input SCK output Serial clock low-level width tWSKL SCK input SCK output Serial clock high-level width SI setup time (vs. SCK ) SI hold time (vs. SCK ) SCK SO delay time tWSKH SCK input tSRXSK tHSKRX tDSKTX R = 1 k , C = 100pF External clock 420 80 80 210 ns ns ns ns External clock Internal divide-by-eight 420 420 ns ns External clock Internal divide-by-eight 1 420 Condition Internal divide-by-eight MIN. 1 MAX. Unit s s ns tCYK-dependent Serial Operation Symbol SCK output tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input External clock 4T-80 MIN. ns External clock Internal divide-by-eight 4T-80 4T-80 MIN. MIN. ns ns External clock Internal divide-by-eight 8T 4T-80 MIN. MIN. ns ns Condition Internal divide-by-eight Calculation Formula 8T MIN./MAX. MIN. Unit ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 29 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (8/9) Other Operations (TA = -10 to +70 C, VDD = +5 V 10 %, VDD = 0 V) Parameter NMI high-/low-level width INTP0 high-/low-level width INTP1 high-/low-level width INTP2 high-/low-level width INTP3 high-/low-level width INTP4 high-/low-level width INTP5 high-/low-level width INTP6 high-/low-level width RESET high-/low-level width TI high-/low-level width VDD rise/fall time Symbol tWNIH, tWNIL tWIOH, tWIOL tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL tRVD, tFVD Analog noises removed Condition Analog noises removed MIN. 4 1 1 1 1 1 1 1 3.5 1 200 MAX. Unit s s s s s s s s s s s Other tCYK-dependent Operations Symbol tWIOH tWIOL tWI1H tWI1L tWI2H tWI2L tWI3H tWI3L tWI4H tWI4L tWI5H tWI5L tWI6H tWI6L tWTIH tWTIL Calculation formula 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T MIN./MAX. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 30 PD78P324, 78P324(A) (1) PD78P324 Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8V Test point 0.8VDD or 2.2V 0.8V A/D Converter Characteristics (TA = -10 to +70 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD -0.5 V AVDD VDD) Parameter Resolution 4.5 V AVREF AVDD Total errorNote1 Quantization error Conversion time Sampling time Zero-scale errorNote1 tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD 4.5 V AVREF AVDD Full-scale errorNote 1 3.4 V AVREF AVDD 4.5 V AVREF AVDD Non-linear errorNote 1 Analog input voltageNote 2 Analog input impedance Reference voltage AVREF current AVDD supply current A/D converter data retention current VIAN When not sampled RAN When sampled AVREF AIREF AIDD AIDDDR Operation mode AVDDDR = 2.5 V STOP mode AVDDDR=5 V10% 10 50 3.4 1.0 2.0 2 Note 3 AVDD 3.0 6.0 15 V mA mA 3.4 V AVREF AVDD 0 10 144 24 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVDD 3.5 V AVREF AVDD Symbol Condition MIN. 10 0.4 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V M A A Notes 1. Quantization error excluded. 2. When -0.3 V VIAN 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF VIAN AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20k Analog input pin 30pF ( input capacitance included ) 10pF 31 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 C) Parameter Symbol VDD AVDD Supply voltage VPP AVSS Input voltage Output voltage Low-level output current VI VO All output pins IOL Total of all output pins All output pins High-level output current IOH Total of all output pins AVDD > VDD Analog input voltage VIAN Notes 2, 3 VDD AVDD AVDD > VDD A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF TA Tstg VDD AVDD -20 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -40 to +85 -65 to +150 C C mA 90 -1.0 mA mA Notes 1, 2 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 4.0 V V V V mA Condition Rating -0.5 to +7.0 -0.5 to VDD +0.5 Unit V V Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 32 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = -40 to +85 C, VDD = +5 V 10%, VSS = 0 V) Parameter Symbol IIJH1 Positive injection current (VIN > VDD) 1 pin Peak value IIJH2 ANn (n = 0-7) Mean value Peak value IIJH Total of all input pins Mean value IIJL1 Negative injection current (VIN < VSS) 1 pin Peak value IIJL2 ANn (n = 0-7) Mean value Peak value IIJL Total of all input pins Mean value -3 mA -0.3 -40 mA mA -4 mA Input ports other than ANn (n = 0-7) Peak value Mean value 5 -4 -0.4 mA mA mA 1 100 mA mA 3 mA Condition Input ports other than ANn (n = 0-7) Peak value Mean value MIN. TYP. MAX. 10 0.5 Unit mA mA Cautions 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) T | i(t) | 0 3/2 dt)2/3 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency 8MHz fXX 16MHz TA -40 to +85 C VDD +5.0 V 10 % Capacitance (TA = 25 C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz; 0 V except measured pins Condition MIN. TUP. MAX. 10 20 20 Unit pF pF pF 33 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (3/9) Oscillator Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V) Oscillator Recommended Circuit Parameter MIN. MAX. Unit X2 X1 VSS Ceramic oscillator or crystal oscillator C2 C1 Oscillation frequency (fXX) 8 16 MHz X1 X2 HCMOS inverter X1 input frequency (fX) 8 16 MHz External clock X1 or X2 No connection required HCMOS inverter X1 input rise time, fall time (tXR, tXF) X1 input high-/low-level width (tWXH, tWXL) 0 25 20 80 ns ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. * Make the wiring as short as possible. * Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. * Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. * Do not fetch signals from the oscillation circuit. 34 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (4/9) DC Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Low-level input voltage High-level input voltage VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current IDD2 Data retention voltage Data retention current IDDDR STOP mode VDDDR=5.0 V10% 10 50 VDDDR HALT mode STOP mode VDDDR = 2.5 V 2.5 2 10 35 55 mA V VOL VOH ILI ILIAN ILO IDD1 Note 3 Note 4 Note 2 IOL = 2.0mA IOH = -400A 0 V VI VDD 0 V VIAN AVREF VDD-1.0 10 1 10 70 95 0.8 VDD 0.45 V V Symbol VIL VIH1 Note 1 Condition MIN. 0 2.2 V TYP. MAX. 0.8 Unit V A A A mA 0 V VO VDD Operation mode A A Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 35 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (5/9) AC Characteristics (TA = -40 to +85 C, VDD = +5 V 10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter System clock cycle time Address setup time (vs. ASTB ) Address hold time (vs. ASTB ) Address RD delay time RD address float time Address data input time RD data input time ASTB RD delay time Data hold time (vs. RD ) RD address active time RD low-level width ASTB high-level width Address WR delay time ASTB data output time WR data output time ASTB WR delay time Data setup time (vs. WR ) Data hold time (vs. WR ) WR ASTB delay time WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 42 147 32 42 147 42 0 50 147 37 85 102 40 Condition MIN. 125 32 32 85 10 222 112 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 36 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Symbol tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation formula 0.5T-30 0.5T-30 T-40 (2.5+n) T-90 (1.5+n) T-75 0.5T-20 0.5T-12 (1.5+n) T-40 0.5T-25 T-40 0.5T+40 0.5T-20 1.5T-40 0.5T-30 0.5T-20 (1.5+n) T-40 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 37 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (7/9) Serial Operation (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Serial clock cycle time Symbol SCK output tCYSK SCK input SCK output Serial clock low-level width tWSKL SCK input SCK output Serial clock high-level width SI setup time (vs. SCK ) SI hold time (vs. SCK ) SCK SO delay time tWSKH SCK input tSRXSK tHSKRX tDSKTX R = 1 k , C = 100pF External clock 420 80 80 210 ns ns ns ns External clock Internal divide-by-eight 420 420 ns ns External clock Internal divide-by-eight 1 420 Condition Internal divide-by-eight MIN. 1 MAX. Unit s s ns tCYK-dependent Serial Operation Symbol SCK output tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input External clock 4T-80 MIN. ns External clock Internal divide-by-eight 4T-80 4T-80 MIN. MIN. ns ns External clock Internal divide-by-eight 8T 4T-80 MIN. MIN. ns ns Condition Internal divide-by-eight Calculation Formula 8T MIN./MAX. MIN. Unit ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 38 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (8/9) Other Operations (TA = -40 to +85 C, VDD = +5 V 10 %, VDD = 0 V) Parameter NMI high-/low-level width INTP0 high-/low-level width INTP1 high-/low-level width INTP2 high-/low-level width INTP3 high-/low-level width INTP4 high-/low-level width INTP5 high-/low-level width INTP6 high-/low-level width RESET high-/low-level width TI high-/low-level width VDD rise/fall time Symbol tWNIH, tWNIL tWIOH, tWIOL tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL tRVD, tFVD Analog noises removed Condition Analog noises removed MIN. 4 1 1 1 1 1 1 1 3.5 1 200 MAX. Unit s s s s s s s s s s s Other tCYK-dependent Operations Symbol tWIOH tWIOL tWI1H tWI1L tWI2H tWI2L tWI3H tWI3L tWI4H tWI4L tWI5H tWI5L tWI6H tWI6L tWTIH tWTIL Calculation formula 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T MIN./MAX. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 39 PD78P324, 78P324(A) (2) PD78P324(A) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8V Test point 0.8VDD or 2.2V 0.8V A/D Converter Characteristics (TA = -40 to +85 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD -0.5 V AVDD VDD) Parameter Resolution 4.5 V AVREF AVDD Total errorNote 1 Quantization error Conversion time Sampling time Zero-scale errorNote 1 tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD 4.5 V AVREF AVDD Full-scale errorNote 1 3.4 V AVREF AVDD 4.5 V AVREF AVDD Non-linear errorNote 1 Analog input voltageNote 2 Analog input impedance Reference voltage AVREF current AVDD supply current A/D converter data retention current VIAN When not sampled RAN When sampled AVREF AIREF AIDD AIDDDR Operation mode AVDDDR = 2.5 V STOP mode AVDDDR=5 V10% 10 50 3.4 1.0 2.0 2 Note 3 AVDD 3.0 6.0 15 V mA mA 3.4 V AVREF AVDD 0 10 144 24 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVDD 3.5 V AVREF AVDD Symbol Condition MIN. 10 0.4 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V M A A Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF VIAN AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20k Analog input pin 30pF ( input capacitance included ) 10pF 40 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 C) Parameter Symbol VDD AVDD Supply voltage VPP AVSS Input voltage Output voltage Low-level output current VI VO All output pins IOL Total of all output pins All output pins High-level output current IOH Total of all output pins AVDD > VDD Analog input voltage VIAN Notes 2, 3 VDD AVDD AVDD > VDD A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF TA Tstg VDD AVDD -20 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -40 to +110 -65 to +150 C C mA 90 -1.0 mA mA Notes 1, 2 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 4.0 V V V V mA Condition Rating -0.5 to +7.0 -0.5 to VDD +0.5 Unit V V Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 41 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = -40 to +110 C, VDD = +5 V 10%, VSS = 0 V) Parameter Symbol IIJH1 Positive injection current (VIN > VDD) 1 pin Peak value IIJH2 ANn (n = 0-7) Mean value Peak value IIJH Total of all input pins Mean value IIJL1 Negative injection current (VIN < VSS) 1 pin Peak value IIJL2 ANn (n = 0-7) Mean value Peak value IIJL Total of all input pins Mean value -3 mA -0.3 -40 mA mA -4 mA Input ports other than ANn (n = 0-7) Peak value Mean value 5 -4 -0.4 mA mA mA 1 100 mA mA 3 mA Condition Input ports other than ANn (n = 0-7) Peak value Mean value MIN. TYP. MAX. 10 0.5 Unit mA mA Cautions 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) T | i(t) | 0 3/2 dt)2/3 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency 8MHz fXX 12.5 MHz TA -40 to +110 C VDD +5.0 V 10 % Capacitance (TA = 25 C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O cpapacitance Symbol CI CO CIO f = 1 MHz; 0 V except measured pins Condition MIN. TUP. MAX. 10 20 20 Unit pF pF pF 42 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (3/9) Oscillator Characteristics (TA = -40 to +110 C, VDD = +5 V 10 %, VSS = 0 V) Oscillator Recommended Circuit Parameter MIN. MAX. Unit X2 X1 VSS Ceramic oscillator or crystal oscillator C2 C1 Oscillation frequency (fXX) 8 12.5 MHz X1 X2 HCMOS inverter X1 input frequency (fX) 8 12.5 MHz External clock X1 or X2 No connection required HCMOS inverter X1 input rise time, fall time (tXR, tXF) X1 input high-/low-level width (tWXH, tWXL) 0 46 20 100 ns ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. * Make the wiring as short as possible. * Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. * Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. * Do not fetch signals from the oscillation circuit. 43 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (4/9) DC Characteristics (TA = -40 to +110 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Low-level input voltage High-level input voltage VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current IDD2 Data retention voltage Data retention current IDDDR STOP mode VDDDR=5.0 V10% 10 1000 VDDDR HALT mode STOP mode VDDDR = 2.5 V 2.5 2 100 25 48 mA V VOL VOH ILI ILIAN ILO IDD1 Note 3 Note 4 Note 2 IOL = 2.0mA IOH = -400A 0 V VI VDD 0 V VIAN AVREF VDD-1.0 10 2 10 65 87 0.8 VDD 0.45 V V Symbol VIL VIH1 Note 1 Condition MIN. 0 2.2 V TYP. MAX. 0.8 Unit V A A A mA 0 V VO VDD Operation mode A A Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 44 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (5/9) AC Characteristics (TA = -40 to +110 C, VDD = +5 V 10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter System clock cycle time Address setup time (vs. ASTB ) Address hold time (vs. ASTB ) Address RD delay time RD address float time Address data input time RD data input time ASTB RD delay time Data hold time (vs. RD ) RD address active time RD low-level width ASTB high-level width Address WR delay time ASTB data output time WR data output time ASTB WR delay time Data setup time (vs. WR ) Data hold time (vs. WR ) WR ASTB delay time WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 60 191 50 60 195 60 0 68 191 55 120 120 40 Condition MIN. 160 40 50 120 10 310 165 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Symbol tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation formula 0.5T-40 0.5T-30 T-40 (2.5+n) T-90 (1.5+n) T-75 0.5T-20 0.5T-12 (1.5+n) T-49 0.5T-25 T-40 0.5T+40 0.5T-20 1.5T-49 0.5T-30 0.5T-20 (1.5+n) T-45 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 46 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (7/9) Serial Operation (TA = -40 to +110 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Serial clock cycle time Symbol SCK output tCYSK SCK input SCK output Serial clock low-level width tWSKL SCK input SCK output Serial clock high-level width SI setup time (vs. SCK ) SI hold time (vs. SCK ) SCK SO delay time tWSKH SCK input tSRXSK tHSKRX tDSKTX R = 1 k , C = 100pF External clock 560 80 80 210 ns ns ns ns External clock Internal divide-by-eight 560 560 ns ns External clock Internal divide-by-eight 1280 560 Condition Internal divide-by-eight MIN. 1280 MAX. Unit s s ns tCYK-dependent Serial Operation Symbol SCK output tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input External clock 4T-80 MIN. ns External clock Internal divide-by-eight 4T-80 4T-80 MIN. MIN. ns ns External clock Internal divide-by-eight 8T 4T-80 MIN. MIN. ns ns Condition Internal divide-by-eight Calculation Formula 8T MIN./MAX. MIN. Unit ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 47 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (8/9) Other Operations (TA = -40 to +110 C, VDD = +5 V 10 %, VDD = 0 V) Parameter NMI high-/low-level width INTP0 high-/low-level width INTP1 high-/low-level width INTP2 high-/low-level width INTP3 high-/low-level width INTP4 high-/low-level width INTP5 high-/low-level width INTP6 high-/low-level width RESET high-/low-level width TI high-/low-level width VDD rise/fall time Symbol tWNIH, tWNIL tWIOH, tWIOL tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL tRVD, tFVD Analog noises removed Condition Analog noises removed MIN. 4 1280 1280 1280 1280 1280 1280 1280 3.5 1280 200 MAX. Unit s ns ns ns ns ns ns ns s ns s Other tCYK-dependent Operations Symbol tWIOH tWIOL tWI1H tWI1L tWI2H tWI2L tWI3H tWI3L tWI4H tWI4L tWI5H tWI5L tWI6H tWI6L tWTIH tWTIL Calculation formula 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T MIN./MAX. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 48 PD78P324, 78P324(A) (3) PD78P324(A1) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8V Test point 0.8VDD or 2.2V 0.8V A/D Converter Characteristics (TA = -40 to +110 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD -0.5 V AVDD VDD) Parameter Resolution 4.5 V AVREF AVDD Total errorNote 1 Quantization error Conversion time Sampling time Zero-scale errorNote 1 tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD 4.5 V AVREF AVDD Full-scale errorNote 1 3.4 V AVREF AVDD 4.5 V AVREF AVDD Non-linear errorNote 1 Analog input voltageNote 2 Analog input impedance Reference voltage AVREF current AVDD supply current A/D converter data retention current VIAN When not sampled RAN When sampled AVREF AIREF AIDD AIDDDR Operation mode AVDDDR = 2.5 V STOP mode AVDDDR=5 V10% 10 1000 3.4 1.0 2.0 2 Note 3 AVDD 3.0 6.0 100 V mA mA 3.4 V AVREF AVDD 0 10 144 24 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVDD 3.5 V AVREF AVDD Symbol Condition MIN. 10 0.4 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V M A A Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF VIAN AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20k Analog input pin 30pF ( input capacitance included ) 10pF 49 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (1/9) Absolute Maximum Ratings (TA = 25 C) Parameter Symbol VDD AVDD Supply voltage VPP AVSS Input voltage Output voltage Low-level output current VI VO All output pins IOL Total of all output pins All output pins High-level output current IOH Total of all output pins AVDD > VDD Analog input voltage VIAN Notes 2, 3 VDD AVDD AVDD > VDD A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF TA Tstg VDD AVDD -20 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -0.5 to VDD +0.5 V -0.5 to AVDD +0.5 -40 to +125 -65 to +150 C C mA 90 -1.0 mA mA Notes 1, 2 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD +0.5 -0.5 to VDD +0.5 4.0 V V V V mA Condition Rating -0.5 to +7.0 -0.5 to VDD +0.5 Unit V V Notes 1. Except P70/AN0-P77/AN7. 2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application is excluded. 3. P70/AN0-P77/AN7 pins. Caution If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the quality of the product may be degraded. In other words, the product may be physically damaged if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding these ratings. 50 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (2/9) Permissible Pin Injection Current Characteristics in Overvoltage Application (TA = -40 to +125 C, VDD = +5 V 10%, VSS = 0 V) Parameter Symbol IIJH1 Positive injection current (VIN > VDD) 1 pin Peak value IIJH2 ANn (n = 0-7) Mean value Peak value IIJH Total of all input pins Mean value IIJL1 Negative injection current (VIN < VSS) 1 pin Peak value IIJL2 ANn (n = 0-7) Mean value Peak value IIJL Total of all input pins Mean value -3 mA -0.3 -40 mA mA -4 mA Input ports other than ANn (n = 0-7) Peak value Mean value 5 -4 -0.4 mA mA mA 1 100 mA mA 3 mA Condition Input ports other than ANn (n = 0-7) Peak value Mean value MIN. TYP. MAX. 10 0.5 Unit mA mA Cautions. 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion result of the analog input contiguous to the current injection pin has the value of the standard in which the injection current is not running plus 2LSB. 2. The mean value (absolute value) of the pin injected current is as follows: Mean value = ((1/T) T | i(t) | 0 3/2 dt)2/3 In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value. Recommended Operating Range Oscillation Frequency 8MHz fXX 12.5 MHz TA -40 to +125 C VDD +5.0 V 10 % Capacitance (TA = 25 C, VSS = VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz; 0 V except measured pins Condition MIN. TUP. MAX. 10 20 20 Unit pF pF pF 51 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (3/9) Oscillator Characteristics (TA = 40 to +125 C, VDD = +5 V 10 %, VSS = 0 V) Oscillator Recommended Circuit Parameter MIN. MAX. Unit X2 X1 VSS Ceramic oscillator or crystal oscillator C2 C1 Oscillation frequency (fXX) 8 12.5 MHz X1 X2 HCMOS inverter X1 input frequency (fX) 8 12.5 MHz External clock X1 or X2 No connection required HCMOS inverter X1 input rise time, fall time (tXR, tXF) X1 input high-/low-level width (tWXH, tWXL) 0 46 20 100 ns ns Caution When using the system clock oscillation circuit, wire the part encircled in the dotted line in the following manner to avoid the influence of the wiring capacity, etc. * Make the wiring as short as possible. * Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating currents run. * Make sure that the grounding point of the oscillation circuit capacitor always has the same electrical potential as VSS. Avoid grounding with a grand pattern in which very high currents run. * Do not fetch signals from the oscillation circuit. 52 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (4/9) DC Characteristics (TA = -40 to +125 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Low-level input voltage High-level input voltage VIH2 Low-level output voltage High-level output voltage Input leakage current Analog pin input leakage current Output leakage current VDD supply current IDD2 Data retention voltage Data retention current IDDDR STOP mode VDDDR=5.0 V10% 10 1000 VDDDR HALT mode STOP mode VDDDR = 2.5 V 2.5 2 100 25 48 mA V VOL VOH ILI ILIAN ILO IDD1 Note 3 Note 4 Note 2 IOL = 2.0mA IOH = -400A 0 V VI VDD 0 V VIAN AVREF VDD-1.0 10 2 10 65 87 0.8 VDD 0.45 V V Symbol VIL VIH1 Note 1 Condition MIN. 0 2.2 V TYP. MAX. 0.8 Unit V A A A mA 0 V VO VDD Operation mode A A Notes 1. Pins other than pins in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins. 3. Pins except P20/NMI, EA/VPP, X1, X2 4. When not sampling the analog input 53 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (5/9) AC Characteristics (TA = -40 to +125 C, VDD = +5 V 10%, VSS = 0 V, CL = 100pF) Non-serial Read/Write Operation (when connecting general-purpose memory) Parameter System clock cycle time Address setup time (vs. ASTB ) Address hold time (vs. ASTB ) Address RD delay time RD address float time Address data input time RD data input time ASTB RD delay time Data hold time (vs. RD ) RD address active time RD low-level width ASTB high-level width Address WR delay time ASTB data output time WR data output time ASTB WR delay time Data setup time (vs. WR ) Data hold time (vs. WR ) WR ASTB delay time WR low-level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 60 191 50 60 195 60 0 68 191 55 120 120 40 Condition MIN. 160 40 50 120 10 310 165 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 54 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (6/9) tCYK-dependent Bus Timing Definition Symbol tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation formula 0.5T-40 0.5T-30 T-40 (2.5+n) T-90 (1.5+n) T-75 0.5T-20 0.5T-12 (1.5+n) T-49 0.5T-25 T-40 0.5T+40 0.5T-20 1.5T-49 0.5T-30 0.5T-20 (1.5+n) T-45 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. n refers to the count of weight cycles defined by the user software. 3. Among the parameters for bus timing, only those listed in this table are dependent on tCYK. 55 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (7/9) Serial Operation (TA = 40 to +125 C, VDD = +5 V 10 %, VSS = 0 V) Parameter Serial clock cycle time Symbol SCK output tCYSK SCK input SCK output Serial clock low-level width tWSKL SCK input SCK output Serial clock high-level width SI setup time (vs. SCK ) SI hold time (vs. SCK ) SCK SO delay time tWSKH SCK input tSRXSK tHSKRX tDSKTX R = 1 k , C = 100pF External clock 560 80 80 210 ns ns ns ns External clock Internal divide-by-eight 560 560 ns ns External clock Internal divide-by-eight 1280 560 Condition Internal divide-by-eight MIN. 1280 MAX. Unit s s ns tCYK-dependent Serial Operation Symbol SCK output tCYSK SCK input SCK output tWSKL SCK input SCK output tWSKH SCK input External clock 4T-80 MIN. ns External clock Internal divide-by-eight 4T-80 4T-80 MIN. MIN. ns ns External clock Internal divide-by-eight 8T 4T-80 MIN. MIN. ns ns Condition Internal divide-by-eight Calculation Formula 8T MIN./MAX. MIN. Unit ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK. 56 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (8/9) Other Operations (TA = -40 to +125 C, VDD = +5 V 10 %, VDD = 0 V) Parameter NMI high-/low-level width INTP0 high-/low-level width INTP1 high-/low-level width INTP2 high-/low-level width INTP3 high-/low-level width INTP4 high-/low-level width INTP5 high-/low-level width INTP6 high-/low-level width RESET high-/low-level width TI high-/low-level width VDD rise/fall time Symbol tWNIH, tWNIL tWIOH, tWIOL tWI1H, tWI1L tWI2H, tWI2L tWI3H, tWI3L tWI4H, tWI4L tWI5H, tWI5L tWI6H, tWI6L tWRSH, tWRSL tWTIH, tWTIL tRVD, tFVD Analog noises removed Condition Analog noises removed MIN. 4 1280 1280 1280 1280 1280 1280 1280 3.5 1280 200 MAX. Unit s ns ns ns ns ns ns ns s ns s Other tCYK-dependent Operations Symbol tWIOH tWIOL tWI1H tWI1L tWI2H tWI2L tWI3H tWI3L tWI4H tWI4L tWI5H tWI5L tWI6H tWI6L tWTIH tWTIL Calculation formula 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T 8T MIN./MAX. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency) 2. Only the parameters listed in this table depend on tCYK. 57 PD78P324, 78P324(A) (4) PD78P324(A2) Electrical Specifications (9/9) AC Timing Test Point VDD 0V 0.8VDD or 2.2V 0.8V Test point 0.8VDD or 2.2V 0.8V A/D Converter Characteristics (TA = -40 to +125 C, VDD = +5 V 10 %, VSS = AVSS = 0 V, VDD -0.5 V AVDD VDD) Parameter Resolution 4.5 V AVREF AVDD Total errorNote 1 Quantization error Conversion time Sampling time Zero-scale errorNote 1 tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD 4.5 V AVREF AVDD Full-scale errorNote 1 3.4 V AVREF AVDD 4.5 V AVREF AVDD Non-linear errorNote 1 Analog input voltageNote 2 Analog input impedance Reference voltage AVREF current AVDD supply current A/D converter data retention current VIAN When not sampled RAN When sampled AVREF AIREF AIDD AIDDDR Operation mode AVDDDR = 2.5 V STOP mode AVDDDR=5 V10% 10 1000 3.4 1.0 2.0 2 Note 3 AVDD 3.0 6.0 100 V mA mA 3.4 V AVREF AVDD 0 10 144 24 1.5 1.5 1.5 1.5 1.5 1.5 2.5 4.5 2.5 4.5 2.5 4.5 AVDD 3.5 V AVREF AVDD Symbol Condition MIN. 10 0.4 0.7 1/2 TYP. MAX. Unit bit %FSR %FSR LSB tCYK tCYK LSB LSB LSB LSB LSB LSB V M A A Notes 1. Quantization error excluded. 2. When VIAN = 0 V, the conversion result becomes 000H. When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits. When AVREF VIAN AVDD, the conversion result is 3FFH. 3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram below. (The values in the diagram are TYP. values; therefore, they are not assured.) 20k Analog input pin 30pF ( input capacitance included ) 10pF 58 PD78P324, 78P324(A) Non-serial Read Operation tCYK (CLK) P50-P57 (Output) Hi-Z Upper address tDAID tSAST Lower address(Output) tWSTH Upper address P40-P47 (Input/Output) Hi-Z Data (Input) tHRID Hi-Z Lower address(Output) Hi-Z ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDAR tWRL tDRA Non-serial Write Operation (CLK) P50-P57 (Output) tSAST P40-P47 (Input/Output) Lower address(Output) tWSTH ASTB (Output) tHSTA Upper address Upper address Undfined Data (Output) tHWOD Lower address(Output) tDWST tDSTOD WR (Output) tDSTW tDWOD tDAW tWWL tSODW 59 PD78P324, 78P324(A) Serial Operation tCYSK tWSKL SCK tDSKTX SO tWSKH SI tSRXSK tHSKRX Interrupt Input Timing tWNIH tWNIL NMI 0.8VDD 0.8V tWInH tWInL 1NTPn Remark n = 0-6 60 PD78P324, 78P324(A) Reset Input Timing tWRSH tWRSL RESET 0.8VDD 0.8V TI Pin Input Timing tWTIH tWTIL TI Data Retention Timing 90% VDD 10% VDDDR tFVD tRVD 61 PD78P324, 78P324(A) DC Programming Characteristics (TA = 25 5 C, VSS = 0 V) Parameter High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage Input current Output leakage current VDDP supply voltage Symbol VIH VIL ILI VOH VOL IA9 ILO VDDP SymbolNote 1 VIH VIL ILI VOH VOL -- -- VCC Program memory Read mode Program memory Write mode VPP supply voltage VPP VPP Program memory Read mode Program memory Write mode VDDP supply current IDD IDD Program memory Read mode Program memory Write mode CE = PGM VPP supply current IPP IPP Program memory Read mode VPP = VDD 1 100 50 50 mA mA VPP = VDDP 30 V mA 4.5 12.2 5.0 12.5 5.5 12.8 V V 0 VI VDDPNote 2 IOH = -400 A IOL = 2.0 A A9(P20/NMI) pin, 0 VO VDDP 0 VO VDDP, OE = VIH Program memory Write mode 6.25 65 2.4 0.45 10 10 6.75 Condition MIN. 2.4 -0.3 TYP. MAX. VDDP+0.3 0.8 10 Unit V V A V V A A V A Notes 1. Refers to the symbol of the corresponding PD27C1001A. 2. VDDP refers to the VDD pin in programming. 62 PD78P324, 78P324(A) AC Programming Characteristics (TA = 255 C, VSS = 0 V) In PROM Write Mode Parameter Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time VPP setup time VDDP setup time Initial program pulse width OE set time OE valid data delay time SymbolNote1 tAS tCES tDS tAH tDH tDF tVPS tVDSNote 2 tPW tOES tOE Condition MIN. 2 2 2 2 2 0 2 2 0.095 2 200 0.1 0.105 130 TYP. MAX. Unit s s s s s ns s s ms s ns Notes 1. Corresponds to the symbol of PD27C1001A (tVDS excluded). 2. The symbol of tVDS on PD27C1001A is tVCS. In PROM Read Mode Parameter Address data output time CE data output time OE data output time Data hold time (vs. OE , CE )Note 2 Data hold time (vs. address) SymbolNote1 tACC tCE tOE tDF tOH Condition CE = OE = VIL OE = VIL CE = VIL CE = VIL or OE = VIL CE = OE = VIL 0 0 MIN. TYP. MAX. 2 1 1 130 Unit s s s ns ns Notes 1. Corresponds to the symbol of PD27C1001A. 2. tDF refers to the time when either OE or CE became VIH first. 63 PD78P324, 78P324(A) PROM Write Mode Timing Program A0-A16 tAS D0-D7 VPP VPP VDDP VDDP + 1.5 VDDP VDDP VIH CE VIL VIH PGM VIL VIH OE VIL tOES tOE tCES tPW tVDS tVPS Hi-Z tDS Data input tDH Hi-Z Data output tAH tDF Hi-Z Program verify Cautions 1. Ensure to apply VDDP before VPP, and disconnect it after VPP. 2. Ensure that VPP does not exceed +13.5 V even when the overshoot is included. 3. Taking out or putting in while +12.5 V is applied to VPP may cause adverse effects on the reliability. PROM Read Mode Timing A0-A16 Vailed address CE OE tACC Hi-Z Note 1 tOE Note 1 tDF tOH Data output Note 2 D0-D7 Hi-Z Notes 1. To read within the range of tACC, please make sure that the delay time from CE's falling edge of the OE input is up to tACC-tOE. 2. tDF refers to the time when either OE or CE became VIH first. 64 PD78P324, 78P324(A) 8. PACKAGE DRAWINGS 74-Pin Plastic QFP(s 20) s A B F2 56 57 38 37 detail of lead end C D S F1 74 1 19 18 G1 G2 H I M J K P N NOTE L ITEM A B MILLIMETERS 23.20.4 20.00.2 20.00.2 23.20.4 2.0 1.0 2.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.60.2 0.80.2 0.15+0.10 -0.05 0.10 3.7 0.10.1 55 4.0 MAX. INCHES 0.913 +0.017 -0.016 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.079 0.039 0.079 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S74GJ-100-5BJ-3 Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. Remark The package and material of the ES product are equivalent to those for mass production. M Q C D F1 F2 G1 G2 H I J K L M N P Q R S R 65 PD78P324, 78P324(A) 68 PIN PLASTIC QFJ ( 950 mil) A B F E U G H J T K M N M Q I P C D 68 1 P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 1.0 0.12 23.12 0.20 0.15 R 0.8 0.20 +0.10 -0.05 INCHES 0.992 0.008 0.953 0.953 0.992 0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110+0.009 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 0.910+0.009 -0.008 0.006 R 0.031 0.008+0.004 -0.002 Remark The package and material of the ES product are equivalent to those for mass production. 66 PD78P324, 78P324(A) 74 PIN CERAMIC WQFN A B K Q T D C 74 W Y 1 J E F G R S H I M U X74KW-100A-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W Y MILLIMETERS 20.0 0.4 18.0 18.0 20.0 0.4 1.94 2.14 4.0 MAX. 0.51 0.10 0.10 1.0 (T.P.) 1.0 0.2 C 0.3 2.0 2.0 R 2.0 10.0 0.7 0.2 C 1.5 INCHES 0.787+0.017 -0.016 0.709 0.709 0.787+0.017 -0.016 0.076 0.084 0.158 MAX. 0.020 0.004 0.004 0.039 (T.P.) 0.039 -0.008 C 0.012 0.079 0.079 R 0.079 0.394 0.028 -0.009 C 0.059 +0.008 +0.009 Remark The package and material of the ES product are equivalent to those for mass production. 67 PD78P324, 78P324(A) 68 PIN CERAMIC WQFN A B K L Q P T 68 1 U D C Y H G E F IM J R X68KW-50A-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L P Q R S T U Y MILLIMETERS 24.13 0.4 21.5 21.5 24.13 0.4 1.65 2.03 3.50 MAX. 0.64 0.10 0.12 1.27 (T.P.) 1.27 0.2 2.16 0.2 R 0.2 C 1.02 1.905 1.905 R 3.0 12.0 C 0.5 INCHES 0.950 0.016 0.846 0.846 0.950 0.016 0.065 0.080 0.138 MAX. 0.025+0.005 -0.004 0.005 0.05 (T.P.) 0.05 0.008 0.085 0.008 R 0.008 C 0.04 0.075 0.075 R 0.118 0.472 C 0.020 Remark The package and material of the ES product are equivalent to those for mass production. 68 S PD78P324, 78P324(A) 9. RECOMMENDED SOLDERING CONDITIONS Please solder the package of this product under the conditions recommended as follows. For details of the recommended conditions for soldering, please refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, please contact NEC sales personnel. Table 9-1. Soldering Conditions for Surface-Mount Type (1) PD78P324GJ-5BJ PD78P324LP PD78P324LP(A) PD78P324LP(A1) PD78P324LP(A2) Soldering Method Infrared reflow VPS Wave soldering : 74-pin plastic QFP (20 x 20 mm) : 68-pin plastic QFJ (s 950 mil) s : 68-pin plastic QFJ (s 950 mil) s : 68-pin plastic QFJ (s 950 mil) s : 68-pin plastic QFJ (s 950 mil) s Soldering Condition Recommended Condition Symbol IR30-367-1 VP15-367-1 Package peak temperature : 230 C; time : within 30 secs (210 C or more); count: once; day limit : 7 daysNote (hereafter, pre-baked for 36 hrs at 125 C) Package peak temperature : 215 C; time : within 40 secs (200 C or more); count: once; day limit : 7 daysNote (hereafter, pre-baked for 36 hrs at 125 C) Solder bath temperature: no more than 260 C; time : within 10 secs; count: once; preheating temperature : 120 C max. (package surface temperature); day limit : 7 daysNote (hereafter, pre-baked for 36 hours at 125 C) Pin temperature : no more than 300 C; time : within 3 secs (per device side) WS60-367-1 -- Pin part heating Note Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25 C and no more than 65 %RH. Caution Avoid using multiple soldering methods at the same time (except the pin part heating method). 69 PD78P324, 78P324(A) Table 9-2. Soldering Conditions for Surface-Mount Type (2) PD78P324GJ(A)-5BJ PD78P324GJ(A1)-5BJ PD78P324GJ(A2)-5BJ Soldering Method Infrared reflow : 74-pin plastic QFP (20 x 20 mm) : 74-pin plastic QFP (20 x 20 mm) : 74-pin plastic QFP (20 x 20 mm) Soldering Condition Recommended Condition Symbol Package peak temperature: 235 C; time: within 30 secs (210 C or more); count: twice; day limit: 7 daysNote (hereafter, pre-baked for 36 hrs at 125 C) IR35-367-2 VPS VP15-367-2 Wave soldering WS60-367-1 -- Pin part heating Note Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25 C and no more than 65 %RH. Caution Avoid using two or more soldering methods at the same time (except the pin part heating method). 70 PD78P324, 78P324(A) APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE INSTALLATION PATTERN Figure A-1. Conversion Socket (EV-9200G-74) Package Drawing (Reference) A E B F M N O R Q S D C T K EV-9200G-74 C 1.5 1 No.1 pin index P J EV-9200G-74-G0 ITEM A G H I B C D E F G H I J K L M N O P Q R S T MILLIMETERS 25.0 20.35 20.35 25.0 4-C 2.8 1.0 11.0 22.0 24.7 5.0 22.0 24.7 8.0 7.8 2.5 2.0 1.35 0.35 0.1 INCHES 0.984 0.801 0.801 0.984 4-C 0.11 0.039 0.433 0.866 0.972 0.197 0.866 0.972 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005 2.3 1.5 0.091 0.059 L 71 PD78P324, 78P324(A) Figure A-2. Recommended Pattern for Conversion Socket (EV-9200G-74) Substrate Installation (Reference) G J D E F K C B A EV-9200G-74-P0 ITEM A B C D E F G H I J K Caution MILLIMETERS 25.7 21.0 INCHES 1.012 0.827 1.00.02 x 18=18.00.05 0.039+0.002 x 0.709=0.709 +0.002 -0.001 -0.003 1.00.02 x 18=18.00.05 0.039+0.002 x 0.709=0.709 +0.002 -0.001 -0.003 21.0 25.7 11.00 0.08 5.00 0.08 0.6 0.02 0.827 1.012 0.433+0.004 -0.003 0.197+0.003 -0.004 0.024+0.001 -0.002 2.36 0.03 1.57 0.03 0.093+0.001 -0.002 0.062+0.001 -0.002 Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207). 72 I H PD78P324, 78P324(A) APPENDIX B. TOOLS B.1 DEVELOPMENT TOOLS The following development tools have been made available for development of the system using the PD78P324. Language Processors 78K/III series relocatable assembler (RA78K/III) Refers to the relocatable assembler which can be used commonly for the 78K/III series. Equipped with the macro function, the relocatable assembler is aimed at improved development efficiency. The assembler is also accompanied by the structured assembler which can describe the program control structure explicitly, thus making it possible to improve the productivity and the maintainability of the program. Host machine OS PC-9800 series IBM PC/ATTM and its compatible machine HP9000 series 300TM SPARCstationTM 78K/III series C compiler (CC78K/III) MS-DOSTM 5-inch 2HD 3.5-inch 2HC PC DOSTM 5-inch 2HC HP-UXTM SunOSTM Cartridge tape (QIC-24) Supply medium 3.5-inch 2HD Part number S5A13RA78K3 S5A10RA78K3 S7B13RA78K3 S7B10RA78K3 S3H15RA78K3 S3K15RA78K3 Refers to the C compiler which can be commonly used in the 78K/III series. This compiler is a program converting the programs written in the C language to those object codes which are executable by microcomputers. When using this compiler, the 78K/III series relocatable assembler (RA78K/III) is required. Host machine OS PC-9800 series IBM PC/AT and its compatible machine HP9000 series 300 SPARCstation MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC HP-UX SunOS Cartridge tape (QIC-24) Supply medium 3.5-inch 2HD Part number S5A13CC78K3 S5A10CC78K3 S7B13CC78K3 S7B10CC78K3 S3H15CC78K3 S3K15CC78K3 Remark Relocatable assembler and C compiler operations are assured only on the host machine and the OS above. 73 PD78P324, 78P324(A) PROM Write Tools Hardware PG-1500 This PROM programmer is capable of programming by manipulating a PROMincorporated single-chip microcomputer from a stand-alone or host machine after connecting the accompanying board and the separately available programmer adapter. It can also program representative PROMs ranging from 256 Kbits to 4 Mbits. These are PROM programmers made by Data I/O Japan. UNISITE 2900 3900Note PA-78P324GJ PA-78P324LP PA-78P324KC PA-78P324KD Software PG-1500 controller These are the PROM programmer adapters for writing programs into the PD78P324 on general-purpose PROM programmer such as PG-1500. PA-78P324GJ: for PD78P324GJ PA-78P324LP: for PD78P324LP PA-78P324KC: for PD78P324KC PA-78P324KD: for PD78P324KD A PG-1500 and a host machine are connected with the serial interface or the parallel interface to control the PG-1500 on the host machine. Host machine OS PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 Note Being evaluated. The PG-1500 controller operation is assured only on the host machine and the OS above. Remark 74 PD78P324, 78P324(A) Debugging Tools Hardware IE-78327-R IE-78320-RNote These are the in-circuit emulators which can be used for the development and debugging of application systems. Debugging is performed by connecting them to a host machine. The IE-78327-R can be used commonly for both the PD78322 subseries and the PD78328 subseries. The IE-78320-R can be used for the PD78322 subseries. These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a target system. EP-78320GJ-R: for 74-pin plastic QFP EP-78320L-R: for 68-pin plastic QFJ This program is for controlling the IE-78327-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine OS PC-9800 series IBM PC/AT and its compatible machine Software IE-78320-R control programNote (IE controller) MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number EP-78320GJ-R EP-78320L-R IE-78327-R control program (IE controller) S5A13IE78327 S5A10IE78327 S7B13IE78327 S7B10IE78327 This program is for controlling the IE-78320-R from a host machine. It can execute commands automatically, thus enabling more efficient debugging. Host machine OS PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13IE78320 S5A10IE78320 S7B10IE78320 Remarks 1. The operation of each software is assured only on the host machine and the OS above. 2. PD78322 subseries: PD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1), 78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2) PD78328 subseries: PD78327, 78328, 78P328, 78327(A), 78328(A) Note The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit emulator, please use the alternative product IE-78327-R. 75 PD78P324, 78P324(A) Development Tool Configurations Host machine PC-9800 series IBM PC/AT or its compatible machine RS-232-C Emulation probes IE-78327-R in-circuit emulator Software RS-232-C EP-78320GJ-R PROM programmer Relocatable assembler (With structured assembler) PG-1500 controller IE controller EP-78320L-R Socket for connecting the emulation probe and the target system Note PG-1500 PROM-incorporated products EV-9200G-74 Socket for plastic QFJ PD78P324GJ PD78P324LP PD78P324KC PD78P324KD + + + Programmer adapters Target system PA-78P324GJ PA-78P324LP PA-78P324KC PA-78P324KD Note The socket is supplied with the emulation probe. 1. It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS232-C. 2. In the diagram above, representative software supply media and 3.5-inch FDs. Remarks 76 PD78P324, 78P324(A) B.2 EVALUATION TOOLS To evaluate the functions of the PD78P324, the following tools are made available. Part Number EB-78320-98 Host Machine PC-9800 series Function By connecting to a host machine, it is possible to evaluate the functions equipped by the PD78P324 in a simple manner. The command system of this product basically conforms to that of IE-78327-R and IE-78320R. Therefore, it is easy to move to the development work of application systems by IE-78327-R or IE-78320-R. In addition a turbo access manager (PD71P301)Note can be mounted on the board. EB-78320-PC IBM PC/AT or its compatible machine Note The turbo access manager (PD71P301) is a maintenance product. 1. This product is not a development tool of PD78P324 application systems. 2. This product is not equipped with the emulation function for executing the PROM incorporated in the PD78P324. Cautions B.3 EMBEDDED SOFTWARE The following embedded software programs are available to perform program development and maintenance more efficiently. Eeal-time OS Real-time OS (RX78K/III) The RX78K/III is designed to provide a multi-task environment in the field of control application where real-time operation is required. By using this real-time OS, the performance of the whole system can be improved by allocating CPU's idle time to other processings. The RX78K/III provides the system call based on the ITRON specifications. The RX78K/III package provides tools (configurators) for creating RX78K/III's nucleus and multiple information table. Host machine OS PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13RX78320 S5A10RX78320 S7B13RX78320 S7B10RX78320 Caution To purchase the operating system above, you need to fill in a purchase application form beforehand and sign a contract allowing you to use the software. Remark When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well. 77 PD78P324, 78P324(A) Fuzzy Inference Development Support System Fuzzy knowledge data creation tools (FE9000, FE9200) This program supports inputting/editing/evaluating (through simulation) of the fuzzy knowledge data (fuzzy rules and membership functions). Host machine OS PC-9800 series IBM PC/AT and its compatible machine Translator (FT78K3)Note MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS Winsows 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FE9000 S5A10FE9000 S7B13FE9000 S7B10FE9000 This program converts the fuzzy knowledge data obtained with fuzzy knowledge data creation tools to an assembler source program for RA78K/III. Host machine OS PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FT78K3 S5A10FT78K3 S7B13FT78K3 S7B10FT78K3 Fuzzy inference module (FI78K/III)Note This program executes fuzzy inference. Fuzzy inference is executed by being linked to the fuzzy knowledge data converted by the translator. Host machine OS PC-9800 series IBM PC/AT and its compatible machine Fuzzy inference debugger (FD78K/III) MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FI78K3 S5A10FI78K3 S7B13FI78K3 S7B10FI78K3 This is a support software program for evaluating and adjusting the fuzzy knowledge data at a hardware level by using the in-circuit emulator. Host machine OS PC-9800 series IBM PC/AT and its compatible machine MS-DOS 5-inch 2HD 3.5-inch 2HC PC DOS 5-inch 2HC Supply medium 3.5-inch 2HD Part number S5A13FD78K3 S5A10FD78K3 S7B13FD78K3 S7B10FD78K3 Note Under development 78 PD78P324, 78P324(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corp. PC/AT and PC DOS are trademarks of IBM Corp. HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 79 PD78P324, 78P324(A) The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78P324KC, 78P324KD The customer must judge the need for license: PD78P324GJ-5BJ/(A)/(A1)/(A2)/, 78P324LP/(A)/(A1)/(A2) No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 |
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